How to make a photonic integrated circuit (PIC) chip?
Photonics is one of the enabling technologies of the future. Light is the fastest information carrier in the universe, and can transmit this information while dissipating less heat and energy than electrical signals. As a result, photonics can greatly improve the speed, coverage and flexibility of communication networks and cope with the ever-increasing demand for more data. And, it will do so at lower energy costs, reducing the internet’s carbon footprint. At the same time, fast and efficient photonic signals have great potential for sensing and imaging applications in medical devices, automotive lidar, agriculture and food diagnostics, etc.
Given its importance, we would like to explain how photonic integrated circuits (PICs), the chips that enable all these applications, are made.
Design a PIC chip
The process of designing a PIC is the transformation of an initial application concept into a manufacturable functional photonics chip. In a short course at the OFC 2018 conference, Wim Bogaerts from Ghent University summarized the typical PIC design process, and we describe the steps in this article.
Figure 1: Steps in the PIC Design Flow
1. Concept and specification. We start by defining what is in the chip. Chip architects typically spend time talking to customers about what they want to achieve with the chip, and all the conditions and situations in which the chip will be used. After these conversations, the chip application concept becomes a set of specific specifications and is passed on to the chip design team. These specifications will set the performance metrics for the PIC design.
2. Design function. After the specifications are established, the design team develops a schematic circuit diagram that captures the functionality of the PIC. This diagram is divided into several functional blocks: some of them may already exist, others may need to be built. These modules include lasers, modulators, detectors and other components that can manipulate light in some way.
3. Design simulation. Making a chip takes a lot of money and time. Faced with such risks, an essential element of chip design is to accurately predict how the chip will behave after fabrication. Functional blocks are put together and their behavior simulated using various physical models and simulation tools. Design teams often use a number of different simulation methods to reduce the risk of failure after manufacturing.
4. Design the layout. Now, the design team must translate the functional chip schematic into an appropriate design layout for manufacturability. Layouts consist of layers, component locations, and geometries that represent actual manufacturing steps. The team uses software to translate these features into the geometry to be manufactured, requiring human intervention for the trickiest placement and geometry decisions.
5. Check the design rules. Each chip fab will have its own set of manufacturing rules. In this step, the design team verifies that the layout complies with these rules.
6. Verify the design function. This is a final check to ensure that the layout was actually performed according to the original schematic. The layout process often results in new component placement and parasitics that were not accounted for in the original schematic. These tests may require the design team to revisit previous functional or layout schematic steps.
Many steps of PIC chip manufacturing
Manufacturing semiconductor chips used in photonics and electronics is one of the most complex processes in the world. For example, Boudewijn Docter, president of EFFECT Photonics, described a chip manufacturing process with a total of 243 steps in his college days.
Jiao Yuqing, an associate professor at the Eindhoven University of Technology (TU/e), explains the manufacturing process in a few basic, simplified steps:
1. Grow or deposit your chip material
2. Print a pattern on the material
3. Etching the pattern on the material
4. Do some cleaning and additional surface preparation
5. Go back to step 1 and repeat as needed
Of course, the actual process is much more complicated, requiring dozens of cycles in the above steps, resulting in a total of more than 200 steps. Let’s look at these basic steps in more detail.
Figure 2: Basic steps in the semiconductor manufacturing process, which are repeated during a manufacturing cycle. The entire wafer fabrication process requires dozens of such cycles.
1. Layered epitaxy and deposition. Different chip devices require different layers of semiconductor material. These layers can be grown on semiconductor wafers by a process called epitaxy, or deposited by other methods.
Figure 3: Simplified example of a device on a PIC chip and the different material layers it requires. Source: Smit et al. (2014)
2. Photolithography (ie printing). There are several lithography methods, but the one used for high-volume chip fabrication is projection optics lithography. Semiconductor wafers are coated with a light-sensitive polymer film called photoresist. At the same time, the designed layout pattern is transferred onto an opaque material called a mask. An optical lithography system projects the mask pattern onto the photoresist. The exposed photoresist is then developed (like photographic film) to complete the pattern printing.
Figure 4: Comparison of different optical lithography methods. Contact and proximity printing place the reticle in contact with or near the sample. Projection lithography keeps the mask farther away and is initially more expensive, but it is the technology of choice for high-volume manufacturing. Source: University of Waterloo J: J. Shen, University of Waterloo PhD dissertation (2018)
3. Etching: After the pattern is “printed” on the photoresist, part of the semiconductor material needs to be removed (or etched) in order to transfer the pattern from the photoresist to the wafer. There are several techniques that can be used to etch materials.
Figure 5: Example of a semiconductor wafer with resist (red) on it, before and after the etching step.
4. Cleaning and surface preparation. After etching, a series of steps clean and prepare the surface before the next cycle.
Passivation. Layers of dielectric material, such as silicon dioxide, are added to “passivate” the chip, making it more resistant to the environment.
Planarization. Planarizes the surface in preparation for future photolithography and etching steps.
Metalization. Deposit metal components and thin films on the wafer. This could be for future photolithography and etching steps, or to add electrical contacts to the chip at the end.
Figure 6 summarizes an InP photonic device after the steps of layer epitaxy, etching, dielectric deposition and planarization and metallization.
Figure 6: Cross-section of a semiconductor wafer structure: (a) epitaxial growth, (b) etching, (c) passivation and planarization, (d) metallization.
Expensive testing and packaging process for PIC chips
Chip manufacturing is a process with many variables, so extensive testing is required to ensure that the manufactured chip is consistent with the original design and simulation. Once this is certified and qualified, the next step is the process of PIC packaging.
While the cost of packaging and testing is a fraction of the cost of electronic systems, the opposite is true for photonic systems. Researchers at the Technical University of Eindhoven (TU/e) estimate that for most indium phosphide (InP) photonic devices, the cost of packaging and testing can reach around 80% of the total module cost. There is a lot of research work going on to reduce these costs.
Figure 7. Breakdown of process costs for InP-based PIC chips, and as a percentage of total manufacturing costs. Source: Latkowski et al., 2019
Especially after the first tapeout of a new chip, there are several rounds of feature extraction, verification, and revision to ensure that the chip performs to specification. After this first round of characterization and verification, the chip must be ready for mass production, which requires a series of reliability tests under several different environmental conditions. For example, different applications require different certifications for the chip’s operating temperature.
Table 1: Comparing temperature ranges for different temperature hardening standards, including industrial, automotive, and full-blown military applications
Summarize
The process of making photonic integrated circuits is very long and complicated, and the steps described in this article are just a simplification of the whole process. It requires a great deal of knowledge in chip design, manufacturing and testing from experts in different fields all over the world.
